Si via interconnection technique for 3D MEMS package

A novel Si via interconnection technique using the doped silicon as an interconnection material is presented for 3D MEMS package. Concept and key idea of silicon via is described. Two layers stacked via arrays with 40 mum and 50 mum spacing are fabricated to prove its feasibility. SDB (silicon direct bonding) multi-stacking process is used for fabrication of stacked package, which consists of a substrate, MEMS structure layer and a cover layer. Resistance of the via which has 34 mum width is measured. Additional electrical and mechanical characteristics of fabricated via are under testing.