Title :
BISTing switched-current circuits
Author :
Renovell, M. ; Azaïs, F. ; Bodin, J.C. ; Bertrand, Y.
Author_Institution :
Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Abstract :
In this paper, a BIST scheme is proposed that applies to any kind of SI building blocks constituted of an aggregate of identical memory cells. The fundamental idea is to reconfigure the building block into a cascade of memory cells so that the output current is equal in magnitude to the input current. Using a very simple circuitry, an error current can then easily be generated that permits one to detect faults in the block
Keywords :
analogue integrated circuits; analogue processing circuits; analogue storage; built-in self test; fault location; integrated circuit testing; integrating circuits; switched current circuits; BIST scheme; SI building blocks; SI integrator; SI memory cells; error current; fault detection; memory cell cascade; switched-current circuits; Aggregates; Built-in self-test; Capacitors; Circuit testing; Clocks; Integrated circuit interconnections; MOS devices; MOSFETs; Output feedback; Rain; Robots; Silicon compounds; Switches; Switching circuits; Voltage;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741641
