High accurate timestamping by phase and frequency estimation

When using network synchronization protocols like IEEE 1588 or NTP, a common approach to increase the performance is to add hardware support for timestamping the essential synchronization messages. Further, timestamping accuracy and the stability of the local oscillator of a network synchronized node are the two main influence factors for high accuracy clock synchronization. While the latter is subject to manufacturing technologies, the first is mainly given by the design of the packet timestamper of the node. While common solutions use sampling in minimized intervals to achieve high accuracy, this paper lists other approaches and proposes a method based on phase/frequency estimation. While the additional hardware effort is rather low, the presented method allows for high accuracy. The performance of the developed design is equivalent to a 5.5 GHz sampling clock, but still can be implemented even in low cost digital logic devices.