A ring architecture strategy for BIST test pattern generation

This paper presents a new effective BIST scheme that achieves 100% fault coverage with low hardware overhead, and without any mollification of the circuit under test, i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator (e.g. an LFSR) is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very simply and with low silicon area cost, without the need of any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length