Test generation for synchronous sequential circuits to reduce storage requirements

The use of appropriate storage schemes for test patterns and test responses on a tester may result in reduced memory requirements, and thus reduced tester cost. Such storage schemes result in new test compaction objectives beyond the need to reduce the number of test patterns as much as possible. We propose test generation procedures that take such test compaction objectives into account. Experimental results are presented to demonstrate the effectiveness of the proposed procedures in reducing the storage requirements of the resulting test sequences