DocumentCode
2497704
Title
A test pattern generation algorithm exploiting behavioral information
Author
Chiusano, Silvia ; Corno, Fulvio ; Prinetto, Paolo
Author_Institution
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
fYear
1998
fDate
2-4 Dec 1998
Firstpage
480
Lastpage
485
Abstract
This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level. The main problem of using behavioral information for ATPG is the mismatch of timing models between the behavioral- and gate-levels. Theoretical analysis shows that the definition of the concept of dominated sequences captures the needed link between the levels. To validate the concept correctness, and to show how it can be profitably exploited, a prototypical hierarchical ATPG is presented, and experimental results show that the performance of a simple ATPG algorithm that is able to exploit behavioral information is much higher than a much more sophisticated gate-level tool
Keywords
automatic test pattern generation; binary sequences; circuit analysis computing; integrated circuit testing; logic testing; timing; behavioral information; dominated sequences; hierarchical ATPG; test pattern generation algorithm; timing models; Automatic test pattern generation; Circuit faults; Circuit synthesis; Circuit testing; Clocks; Control system synthesis; Data mining; Hardware; Performance evaluation; Prototypes; System testing; Test pattern generators; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
ISSN
1081-7735
Print_ISBN
0-8186-8277-9
Type
conf
DOI
10.1109/ATS.1998.741660
Filename
741660
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