Title :
Test pattern generation for column compression multiplier
Author :
Zeng, Pingying ; Mao, Zhigang ; Ye, Yizheng ; Deng, Yuliang
Author_Institution :
Microelectron. Center, Harbin Inst. of Technol., China
Abstract :
When used as the building cell of a parallel multiplier, the (4,2) counter tree is better suited than a Wallace tree for a VLSI implementation because of its more regular structure. In this paper test pattern generation for the CC multipliers is presented following a brief introduction to the structure of the (4,2) counter and the column compression multiplier using a (4,2) counter as its building cell. In conclusion, less test patterns are enough to exhaustively test the CC multiplier
Keywords :
VLSI; automatic test pattern generation; integrated circuit testing; logic testing; multiplying circuits; parallel architectures; (4,2) counter tree; VLSI implementation; building cell; column compression multiplier; exhaustive test; parallel multiplier; regular structure; test pattern generation; Application software; Buildings; Circuit testing; Computer applications; Counting circuits; Digital signal processing; Electronic switching systems; Encoding; Microelectronics; Test pattern generators; Very large scale integration;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741663
