Title :
New domino logic designs for static outputs in evaluation phase for high frequency inputs
Author :
Mohan, Y.K. ; Pandey, Akhilesh Kumar ; Singh, R.K. ; Nagaria, R.K.
Author_Institution :
Dept. of Electron. & Commun. Eng., Motilal Nehru Nat. Inst. of Technol., Allahabad, India
Abstract :
Robustness of domino circuit degrades with the downscaling of the device as leakage power increased. In this paper, we proposed different domino logic styles which improve the performance and also is capable of providing static output in the evaluation phase. According to the simulations in cadence virtuoso 180nm CMOS process, the proposed circuit shows the improvement of up to 50% compared to conventional domino logic circuits.
Keywords :
CMOS logic circuits; logic circuits; logic design; cadence virtuoso CMOS process; conventional domino logic circuits; domino circuit; domino logic designs; domino logic styles; evaluation phase; high frequency inputs; leakage power; robustness; static outputs; CMOS integrated circuits; Clocks; Delays; Discharges (electric); Logic gates; Power dissipation; Transistors; dynamic gates; evaluation phase; pre-charge phase; robustness; static gates;
Conference_Titel :
Engineering and Systems (SCES), 2013 Students Conference on
Conference_Location :
Allahabad
Print_ISBN :
978-1-4673-5628-2
DOI :
10.1109/SCES.2013.6547515
