FPGA timing, power, signal integrity and other challenges at 65 and 45 nm

Summary form only given. The steady march towards smaller feature sizes has made ASIC design, modeling and verification increasingly more challenging. FPGAs present an even greater challenge, since this analysis work must be performed on the user desktop, at the push of a button and for any design, without over-burdening users with the details. In this talk, I will present a brief overview of a few of the modeling, analysis and optimization challenges Altera has faced and overcome on 65nm and 45nm devices. I will touch on modeling and simultaneous optimization across timing corners, hold-time modeling and optimization, on-die variation and jitter, end-of-life effects, metastability analysis, advanced power management techniques, and simultaneous switching noise.