A high performance and highly reliable dual gate CMOS with gate/n/sup -/ overlapped LDD applicable to the cryogenic operation

Author

Inuishi, M. ; Mitsui, K. ; Kusunoki, S. ; Shimizu, M. ; Tsukamoto, K.

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1989

fDate

3-6 Dec. 1989

Firstpage

773

Lastpage

776

Abstract

A dual-gate CMOS structure has been developed which features an overlap LDD (lightly doped drain) NMOS with n/sup +/ poly gate and a surface channel PMOS with p/sup +/ poly gate whose source/drain and gate were salicided with low-resistance TiSi/sub 2/. The gate/n/sup -/ overlapped structure was fabricated by rotational oblique ion implantation. This CMOS structure can realize low-supply-voltage operation due to the small absolute value of threshold voltage without punchthrough. It is demonstrated that, using the overlap LDD NMOS, the circuit speed and the reliability can be improved, compared with the single and the conventional LDD NMOS. The cryogenic operation of the structure is examined.<>

Keywords

CMOS integrated circuits; integrated circuit technology; ion implantation; metallisation; titanium compounds; TiSi/sub 2/; circuit speed; cryogenic operation; dual-gate CMOS structure; gate/n/sup -/ overlapped structure; low-supply-voltage operation; overlap LDD; polycrystalline Si; reliability; rotational oblique ion implantation; salicided metallisation; surface channel PMOS; threshold voltage without punchthrough; Boron; Cryogenics; Heat treatment; Ion implantation; Large scale integration; Low voltage; MOS devices; MOSFETs; Silicidation; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1989.74168

Filename

74168