A system-level stochastic circuit generator for FPGA architecture evaluation

We describe a stochastic circuit generator that can be used to automatically create benchmark circuits for use in FPGA architecture studies. The circuits consist of a hierarchy of interconnected modules, reflecting the structure of circuits designed using a system-on-chip design flow. Within each level of hierarchy, modules can be connected in a bus, star, or dataflow configuration. Our circuit generator is calibrated based on a careful study of existing SoC circuits. We compare our circuits to those generated by previous circuit generators, and characterize our circuits with respect to the type of network used to connect modules.