Title :
An integrated 0.5 mu m CMOS disposable TiN LDD/salicide spacer technology
Author :
Pfiester, J.R. ; Parrillo, L.C. ; Woo, M. ; Kawasaki, H. ; Boeck, B. ; Travis, E. ; Gunderson, C.
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
A novel disposable TiN LDD/salicide spacer process has been developed for a 0.5- mu m CMOS technology. Both LDD (lightly doped drain) and salicide definition are obtained using a single disposable TiN spacer. This process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus n- and boron p-regions for improved short-channel behavior.<>
Keywords :
CMOS integrated circuits; integrated circuit technology; ion implantation; metallisation; 0.5 micron; CMOS technology; Si:B; Si:P; disposable TiN LDD/salicide spacer technology; disposable TiN spacer; lightly doped drain; low salicided junction leakage; reduced lateral diffusion; salicide definition; shallow n-regions; shallow p-regions; short-channel behavior; Annealing; CMOS technology; Etching; Implants; MOS devices; MOSFET circuits; Rapid thermal processing; Space technology; Tin; Titanium;
Conference_Titel :
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1989.74170
