Title :
Optimised single pass connected components analysis
Author :
Ma, Ni ; Bailey, Donald G. ; Johnston, Christopher T.
Author_Institution :
Dept. of ECSE, Monash Univ., Clayton, VIC
Abstract :
Classical connected components labelling algorithms are unsuitable for real-time processing of streamed images on an FPGA because they require two passes through the image. Recently, a single-pass algorithm was proposed that avoided the need to buffer an intermediate image. In this paper, a new single pass algorithm is described that is a considerable improvement over the existing algorithms. The new algorithm reassigns and reuses labels each row to minimise the size of both the equivalence and region data tables. The optimised single-pass algorithm reduces the worst case memory requirement by over 100 times that of the original algorithm (for measuring region area), and reduces the latency to only 1 row.
Keywords :
buffer storage; field programmable gate arrays; image processing; FPGA; classic connected components labelling algorithm; equivalence data table; memory requirement; real-time streamed image processing; region data table; single pass connected components analysis optimisation; Algorithm design and analysis; Area measurement; Corporate acquisitions; Delay; Field programmable gate arrays; Filters; Image analysis; Labeling; Pixel; Streaming media;
Conference_Titel :
ICECE Technology, 2008. FPT 2008. International Conference on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3783-2
Electronic_ISBN :
978-1-4244-2796-3
DOI :
10.1109/FPT.2008.4762382