Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs

Computational fluid dynamics (CFD) is an important tool for aeronautical engineers. Instead of expensive super-computers or clusters, using custom pipelines built on FPGAs is expected to be a cost effective solution to accelerate CFD. The problem is that to keep the pipeline busy is difficult because of the memory bandwidth. To deal with this problem, an effective memory access method using block-RAMs is implemented based on a careful survey about memory access pattern. This work is targetting on two major subroutines in UPACS, a CFD software package. As a result, the amount of data transfer is reduced about 40%. This shows 46-170 fold speed-up is expected by several Virtex-4 FPGAs compared to Itanium2 processor.