Evaluating the impact of customized instruction set on coarse grained reconfigurable arrays

Customizing the instruction set for particular applications has become a successful practice in the industry in the design of application specific processors. Following the same principle, this paper evaluates the impact of embedding specialized instructions within the processing elements (PEs) of coarse grained reconfigurable arrays (CGRAs). We systematically extract and select regular clusters of instructions from the data flow graph of applications. We then embed the selected clusters as specialized instructions within some PEs. We argue that these customized units concentrates the execution of recurrently emerging groups of instructions within a fewer number of PEs. That leads to a more efficient usage of architectural resources, such as control and functional units. Our results demonstrate that arrays with specialized FUs within PEs executes more instructions per area unit and reduce power consumption as compared to architectures where the PEs only contain basic operations. Moreover, we preserve the flexibility of the architecture within the targeted set of applications, which is an important aspect for reconfigurable designs. We show that the adoption of custom instructions in CGRAs retains the typical high instruction parallelism of these architectures with a reduced hardware cost.