Title :
A power improvement technique for a differential LNA
Author :
NarayanaSwamy, M. ; Acharya, Debiprasad Priyabrata
Author_Institution :
Dept. of Electron. & Commun. Eng., NIT, Rourkela, India
Abstract :
This work presents the design of an inductively source degenerated CMOS Differential Low Noise Amplifier (LNA) operating at 2 GHz. LNA is designed using UMC 0.18 μm technology and simulated in Cadence Spectre_RF tool to validate its performance. Power constrained methodology is used for the design of CMOS Differential Low Noise Amplifier. At 1.8V supply voltage, the designed LNA consumed 9mA current. The amplifier provides a power gain (S21) of 22.53dB, noise figure (NFmin) of 1.845dB, S11 of -9.781dB, S12 of -11.42dB and consumes 16.2mW of power.
Keywords :
CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; differential amplifiers; low noise amplifiers; UMC technology; current 9 mA; differential LNA; frequency 2 GHz; gain 22.53 dB; inductively source degenerated CMOS; low noise amplifier; noise figure 1.845 dB; power 16.2 mW; power improvement technique; size 0.18 mum; voltage 1.8 V; CMOS integrated circuits; Gain; Inductors; Integrated circuit modeling; Low-noise amplifiers; Noise; Noise figure; CMOS; Low Noise Amplifier (LNA); noise figure (NF); power;
Conference_Titel :
Engineering and Systems (SCES), 2013 Students Conference on
Conference_Location :
Allahabad
Print_ISBN :
978-1-4673-5628-2
DOI :
10.1109/SCES.2013.6547551
