An implementation of a watershed algorithm based on connected components on FPGA

The watershed transformation is a popular image segmentation technique for gray scale images. In this paper, we describe an implementation method of a watershed algorithm based on connected components on FPGA. In the watershed algorithm based on connected components, regular memory accesses by raster scans and irregular memory accesses using FIFO and stack are repeated. The irregular memory accesses can not be scheduled in advance, and the memory access delay makes it difficult to achieve high performance on hardware systems. In our implementation, large data structures used in the algorithm are placed in the external memory banks redundantly to allow parallel accesses to them, and are accessed as read or write-only to hide the access delay. Frequently accessed small data structures are placed in the internal memory banks, and the accesses to them are arranged so that the maximum parallelism can be exploited. By this data allocation, the access delay to the external memory banks can be hidden, and eight pixels (or four depending on the phase of the algorithm) can be processed in parallel.