Modeling and simulation of low power 14 T full adder with reduced ground bounce noise at 45 nm technology

Static leakage power consumption and ground bounce noise at nanometer scale are becoming most important parameter to kept in consideration are compactness and power which affects the performance use fullness of any VLSI circuits. Full adder is the vital part of digital circuits employing arithmetic operation. Adder circuit is widely used in many digital circuits not only for arithmetic operation but also adder for address generation in processors and microcontrollers. Which are employed in large scale system at higher speed? It is therefore necessary to make these systems more efficient to survive with high speed while consuming low power. As the speed of the circuit increases the most important unwanted parameter that exhibited by the circuits in ground bounce noise. This paper here describes reduction of leakage power and ground bounce noise from the 14T full adder circuits to make it more reliable to be used with high speed system. All the simulation in this paper has been carried out using cadence virtuoso in a 45 nm technology at various voltage and various temperatures.