Title :
Bipolar device design for high density high performance application
Author_Institution :
Plessey Res. Caswell Ltd., Towcester, UK
Abstract :
An analysis of a loaded ECL (emitter coupled logic) gate fabricated in a modern bipolar process shows that the delay is dominated equally by intrinsic and extrinsic components. The design of technology to minimize these components is discussed. As device dimensions are reduced the extrinsic delay components dominate; these components can be minimized by optimizing packing density and using reduced ECL voltage swings. It is suggested that circuits of complexity of 100 K gates and delays of less than 20 ps will be possible in the near future.<>
Keywords :
VLSI; bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; integrated logic circuits; 20 ps; ECL; VLSI; bipolar device design; device dimensions; emitter coupled logic; extrinsic delay; high density high performance; intrinsic delay; load ECL gate; packing density; propagation delay; reduced ECL voltage swings; Boron; Capacitance; Circuits; Delay effects; Helium; Minimization; Performance analysis; Production; Silicon; Wet etching;
Conference_Titel :
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1989.74172
