Title :
Parallel multiplier designs utilizing a non-binary logic scheme
Author_Institution :
Dept. of Comput. Sci., State Univ. of New York, Geneseo, NY, USA
Abstract :
The paper presents a novel approach for CMOS low-power, high performance parallel multiplier design, utilizing a recently proposed non-binary shift switch logic scheme. Compared with the existing well-known parallel multiplier designs, the new approach requires fewer partial product bit reduction stages, and improves performance in speed, VLSI area as well as power dissipation. SPICE simulations with a 0.25 micron, 2.5 volt supply process on critical paths have demonstrated the superiority of the approach
Keywords :
CMOS logic circuits; SPICE; integrated circuit design; logic CAD; multiplying circuits; CMOS low-power high performance parallel multiplier design; SPICE simulations; VLSI area; critical paths; non-binary logic scheme; non-binary shift switch logic scheme; parallel multiplier designs; partial product bit reduction stages; power dissipation; Arithmetic; CMOS logic circuits; Counting circuits; Logic circuits; Logic design; MOSFETs; Power dissipation; Switches; Switching circuits; Very large scale integration;
Conference_Titel :
Euromicro Conference, 2000. Proceedings of the 26th
Conference_Location :
Maastricht
Print_ISBN :
0-7695-0780-8
DOI :
10.1109/EURMIC.2000.874531
