An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs

Field programmable gate arrays (FPGAs) are commonly used as an inexpensive and flexible implementation platform for system-on-chip (SoC) designs. Now that FPGAs are large enough to implement SoCs, the reprogrammable fabric allows a different approach to the design process where on-chip computer aided design (CAD) tools can leverage reconfigurability to reduce design time. Statistics on commercial SoC designs suggest that 50% or more of design time may be spent on testing and verification due to design complexity. In previous work, we have proposed the systems integrating modules with predefined physical links (SIMPPL) SoC architectural framework to improve the design process. The defined communication links and protocols have been used to reduce integration time by an order of magnitude. In this paper, we propose an on-chip testbed that leverages both SIMPPL and an FPGApsilas reconfigurability to enable onchip testing and verification in real time using run time traffic patterns to reduce design time. The proposed testbed requires 331 LUTs and 224 flipflops for the Transmitter and 31 LUTs and 30 flipflops for the receiver. This testbed is able to generate a variety of possible run time traffic patterns that may be used to verify the operation of the CE.