Framework for FPGA–Based Floating Point Discrete-Wavelet Transform Computation Algorithm

The discrete wavelet transform has taken its place at the forefront of research for the development of signal and image processing applications. Hence this paper is proposed on the work of design of hardware for the computation of Floating Point Discrete Wavelet Transform using Harr wavelet. The proposed hardware was implemented using VHDL and components were designed at the gate level. This resulted in an easier synthesizable design. The hardware was synthesized using Xilinx Virtex-4 device. This paper gives us an insight into the making of hardware for computation of DWT using a 32 bit Floating Point Unit. Since all the wavelets except Harr wavelet have their coefficients in floating point representation, a 32 bit FPU was incorporated into the proposed hardware. Typically, synthesis tools are not efficient in designing a memory and the proposed hardware was consisting of two 16K X 32 bit RAM´s. Hence many problems had been faced and solved during the synthesis of this hardware.