Design of High-Rate QC-LDPC Encoder/Decoder for Microwave Radio Systems

A novel decoder architecture is presented for quasi- cyclic low-density parity-check (QC-LDPC) codes. The architecture implements a min-sum algorithm and uses feedback shift-registers to store all the messages exchanged within the algorithm. This shift-register-based min-sum (SRMS) decoder does not require complex interconnections between processors and registers and is amenable to a simple, high throughput hardware implementation. A codec with the SRMS decoder for high-rate codes of length 4095 bits has been fabricated with a 0.15 mum, 1.5 V CMOS technology. The decoder has a gate count of 693 K gates and achieves a throughput of 155.52 Mbps (STM-1) using high-order QAM schemes. Measurement results show that a microwave radio system employing this LDPC codec exhibits good error performance.