Pole-Zero Cancellation Circuit for Charge Sensitive Amplifier with Pile-up Pulses Tracking System

The pole-zero cancellation circuit with pile-up pulses tracking system is discussed. The CSA uses a MOS transistor biased in a triode region to continuous discharge the integration capacitance. The low noise requirements of the front-end electronics place the feedback CSA resistance in hundreds of the MOmega range. However, the high rate of input pulses generates a DC voltage shift at the CSA output and this influences the active feedback circuit. We propose a novel circuit to bias transistors in the feedback of the CSA and in the PZC circuit which tracks the mentioned above voltage shift at the CSA output and ensures the proper cancellation of the CSA feedback pole. We present measurements of a test structure for the continuous CSA feedback discharge and the implementation of this circuit in a fast multichannel ASIC fabricated in the 0.35 mum CMOS technology.