DocumentCode :
2500580
Title :
Automatic effective verification method for distributed and concurrent systems using timed language inclusion
Author :
Yamane, Satoshi
Author_Institution :
Dept. of Comput. Sci., Shimane Univ., Matsue, Japan
fYear :
1997
fDate :
1-3 Apr 1997
Firstpage :
193
Lastpage :
200
Abstract :
We propose a specification and verification method for distributed systems. We can easily specify fairness and timing constraints, and can effectively verify distributed systems by our proposed method. In order to specify fairness, an enable condition and a performed condition are attached to a finite set of states in our proposed specification method. In order to effectively verify distributed systems, we restrict the timing constraints of the timed automaton and specify timing constraints of the clock variables after they are reset to zero. We have developed a verification system based on our proposed method, and have shown its effectiveness with the timed alternating bit protocol
Keywords :
algebraic specification; automata theory; distributed processing; formal specification; program verification; protocols; timing; clock variables; concurrent systems; distributed systems; enable condition; fairness; performed condition; specification method; timed alternating bit protocol; timed automaton; timed language inclusion; timing constraints; verification method; Algebra; Automata; Automatic testing; Cities and towns; Clocks; Computer science; Costs; Formal verification; Protocols; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Real-Time Systems, 1997. Proceedings of the Joint Workshop on
Conference_Location :
Geneva
Print_ISBN :
0-8186-8096-2
Type :
conf
DOI :
10.1109/WPDRTS.1997.637979
Filename :
637979
Link To Document :
بازگشت