Three dimensional ICs, having four stacked active device layers

The four-layer-stacked master slice is proposed as a system application for 3-D ICs. The master slice consists of a programmable logic array for logic circuits, a CMOS gate array for I/O interface buffer circuits, and a CMOS SRAM. Fabrication technologies for the four-layer-stacked 3-D IC are described. Laser beam recrystallization was carried out for the formation of three SOI (silicon-on-insulator) layers in the 3-D IC. Recrystallization without cracks in both SOI and vertical isolation layers was accomplished by adjusting laser annealing conditions. Microprobe Raman spectroscopy data indicated that a tensile stress of (3-6)*10/sup 9/ dyne/cm/sup 2/ was present in each SOI layer. Surface planarization of the vertical isolation layer was carried out with a combination of polystyrene spin coating and dry etching. An initial surface roughness of about 1.7 mu m was successfully reduced to less than 500 A, and the planarized surface did not interfere with either recrystallization or photolithography. NMOSFETs and PMOSFETs, fabricated in the four-layer-stacked 3-D IC, have been successfully operated.<>