The design of random-testable sequential circuits

Author

Wunderlich, H.-J.

Author_Institution

Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., West Germany

fYear

1989

fDate

21-23 June 1989

Firstpage

110

Lastpage

117

Abstract

A method is described for selecting a minimal set of directly accessible flip-flops. Since this problem turns out to be NP-complete, suboptimal solutions can be derived using some heuristics. An algorithm is presented to compute the corresponding weights of the patterns, which are time-dependent in some cases. The entire approach is validated with the help of examples. Only 10-40% of the flip-flops have to be integrated into a partial scan path or into a built-in self-test register to obtain nearly complete fault coverage by weighted random patterns.<>

Keywords

automatic testing; logic testing; sequential circuits; BIST-register; NP-complete; built-in self-test register; design for testability; heuristics; minimal set of directly accessible flip-flops; nearly complete fault coverage; partial scan path; random-testable sequential circuits; suboptimal solutions; weighted random patterns; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Integrated circuit testing; Registers; Sequential analysis; Sequential circuits; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault-Tolerant Computing, 1989. FTCS-19. Digest of Papers., Nineteenth International Symposium on

Conference_Location

Chicago, IL, USA

Print_ISBN

0-8186-1959-7

Type

conf

DOI

10.1109/FTCS.1989.105552

Filename

105552