Title :
Reliable design of high-speed cache and control store memories
Author_Institution :
Tandem Comput. Inc., Cupertino, CA, USA
Abstract :
The design of the cache and control store memories of the Tandem NonStop VLX processor is discussed. Service costs are reduced by using hot-standby sparing to improve the reliability of the large static RAM arrays. Detection, isolation, and spare substitution of failed RAMs are performed automatically without the disruption of normal processing. A control store design with sparing is described. A mathematical model is used to predict reliability improvements for the multiple arrays for each processor board. The model takes into account the selected repair policy which calls for replacing a board only on spare exhaustion or on the failure of nonspared logic. The success of the chosen approach is illustrated through model predictions as well as through field failure data.<>
Keywords :
buffer storage; integrated memory circuits; random-access storage; Tandem NonStop VLX processor; control store memories; high-speed cache; hot-standby sparing; large static RAM arrays; mathematical model; model predictions; multiple arrays; nonspared logic; reliable design; repair policy; service costs; spare substitution; Automatic control; Control systems; Costs; Fault tolerant systems; Frequency; Logic arrays; Power system reliability; Process control; Random access memory; Read-write memory;
Conference_Titel :
Fault-Tolerant Computing, 1989. FTCS-19. Digest of Papers., Nineteenth International Symposium on
Conference_Location :
Chicago, IL, USA
Print_ISBN :
0-8186-1959-7
DOI :
10.1109/FTCS.1989.105576
