Title :
High performance CMOS dual supply level shifter for a 0.5V input and 1V output in standard 1.2V 65nm technology process
Author :
García, José C. ; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid
Author_Institution :
Univ. of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain
Abstract :
This paper presents the design of a highly efficient CMOS level shifter qc-level shifter. Unlike many recent level shifters, the proposed qc-level shifter does not use bootstrap capacitors to minimize active area. When implemented on a 65 nm CMOS technology, under the large capacitive loading condition (2pF), qc-level shifter has a lower active area (94%), and energy-delay product (21.4%) than the reference bootstrap level shifter circuit (ts-level shifter). In comparison to a conventional shifter (c-level shifter)the corresponding reductions are 9.5% and 55%, respectively. Also qc-level shifter has very small effective input capacitance in comparison with ts-level shifter as it does not need a bootstrap capacitor connected to its input.
Keywords :
CMOS integrated circuits; bootstrap circuits; driver circuits; bootstrap capacitor; energy-delay product; high-performance CMOS dual supply level shifter; qc-level shifter; size 65 nm; voltage 0.5 V; voltage 1 V; voltage 1.2 V; CMOS process; CMOS technology; Capacitors; Circuits; Delay; Dynamic voltage scaling; Energy consumption; Energy efficiency; Low voltage; Performance loss;
Conference_Titel :
Communications and Information Technology, 2009. ISCIT 2009. 9th International Symposium on
Conference_Location :
Icheon
Print_ISBN :
978-1-4244-4521-9
Electronic_ISBN :
978-1-4244-4522-6
DOI :
10.1109/ISCIT.2009.5340988