DocumentCode
2502131
Title
A proposal for a fault-tolerant binary hypercube architecture
Author
Chau, S.-C. ; Liestman, A.L.
Author_Institution
Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
fYear
1989
fDate
21-23 June 1989
Firstpage
323
Lastpage
330
Abstract
A modular fault-tolerant binary hypercube architecture is proposed that uses redundant processors and is suitable for use in long-life unmaintained applications. Each module initially contains 2/sup i/ (for any >or=0) active processors and k spare processors and is constructed so that each of the spare processors can replace any of the active processors (or any of the other spares) within the module. Thus, the module can tolerate up to k processor faults. This scheme is compared to previously proposed fault-tolerant binary hypercube architectures. It is shown that the scheme can achieve the same level of reliability as other proposed schemes while using significantly fewer spares.<>
Keywords
fault tolerant computing; parallel architectures; fault-tolerant binary hypercube architecture; redundant processors; reliability; Binary trees; Computer architecture; Fault tolerance; Hypercubes; Multiprocessor interconnection networks; Network topology; Proposals; Redundancy; Reliability engineering; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1989. FTCS-19. Digest of Papers., Nineteenth International Symposium on
Conference_Location
Chicago, IL, USA
Print_ISBN
0-8186-1959-7
Type
conf
DOI
10.1109/FTCS.1989.105587
Filename
105587
Link To Document