Design of a cell library for formal high level synthesis

Author

Sait, Sadiq M. ; Masad-ul-Hasan ; Elleithy, Khalid

fYear

1994

fDate

12-14 Apr 1994

Firstpage

1238

Abstract

In this paper we present a complete design and implementation of a CMOS cell library which supports a formal high level synthesis framework. The library contains the logic level models and VLSI layouts of all primitive functions of the realization specification language (RSL) as well as some commonly used functions which are also built using these basic functions. Modular design methodology is employed to support the expandibility of the basic cells. Example of a formal matrix-matrix multiplier is presented to illustrate the application of the cell library

Keywords

CMOS logic circuits; VLSI; circuit layout CAD; high level synthesis; integrated circuit design; multiplying circuits; specification languages; CMOS cell library; VLSI layouts; basic functions; cell library design; expandibility; formal high level synthesis; formal matrix-matrix multiplier; logic level models; modular design methodology; primitive functions; realization specification language; Circuit simulation; Circuit testing; Computational modeling; Formal specifications; Hardware; High level synthesis; Libraries; Logic; Specification languages; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrotechnical Conference, 1994. Proceedings., 7th Mediterranean

Conference_Location

Antalya

Print_ISBN

0-7803-1772-6

Type

conf

DOI

10.1109/MELCON.1994.380842

Filename

380842