Title :
Systolic interconnection network
Author_Institution :
Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
Abstract :
In this paper, a log2N-stage self-routing rearrangeable network with N inputs/outputs is presented. A self-routing algorithm called the breadth-first destination tag routing algorithm is proposed to realize any permutation of N inputs in a pipelined fashion. This self-routing algorithm maximizes the utilization of every switch of the network, along with a fair load balancing in routing data packets to their destinations. It takes O(log2N) time to realize any permutation of packets on the network. The switch-level and VLSI-level hardware complexities of the network are O(Nlog2N) and O(N 2/log23/2N), respectively
Keywords :
computational complexity; multiprocessor interconnection networks; packet switching; parallel algorithms; systolic arrays; telecommunication network routing; VLSI; breadth-first destination tag; data packets routing; fair load balancing; hardware complexities; multiprocessor interconnection network; packets permutation; self-routing algorithm; self-routing rearrangeable network; systolic interconnection network; Algorithm design and analysis; Computer networks; Genetic mutations; Hardware; Intelligent networks; Multiprocessor interconnection networks; Petroleum; Routing; Sorting; Switches;
Conference_Titel :
Electrotechnical Conference, 1994. Proceedings., 7th Mediterranean
Conference_Location :
Antalya
Print_ISBN :
0-7803-1772-6
DOI :
10.1109/MELCON.1994.380851
