DocumentCode
2502507
Title
Test generation for subtractive specification errors
Author
Lee, Patricia S. ; Harris, Ian G.
Author_Institution
Dept. of Comput. Sci., Univ. of California, Irvine, CA, USA
fYear
2012
fDate
23-25 April 2012
Firstpage
258
Lastpage
263
Abstract
We propose Specification-Based Test Generation (SBTG) which automatically generates functional tests directly from specification, rather than the HDL description of the design. The main benefit of generating tests from the specification is the ability to detect Specification-based Translation Errors (SBTEs) that occur due to a misunderstanding of the specification. Our results show that our test generation approach is more effective at detecting these errors than approaches that generate tests from the HDL code to maximize code coverage metrics.
Keywords
automatic test pattern generation; integrated circuit design; integrated circuit testing; automatic functional IC testing; code coverage metrics; specification-based test generation; specification-based translation error; subtractive specification error; Algorithm design and analysis; Generators; Hardware; Hardware design languages; Production; Timing; HDL; behavioral; coverage metrics; scenario; simulation-based; specification; test generation; testbench; verification;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2012 IEEE 30th
Conference_Location
Hyatt Maui, HI
ISSN
1093-0167
Print_ISBN
978-1-4673-1073-4
Type
conf
DOI
10.1109/VTS.2012.6231063
Filename
6231063
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