Title :
Demonstration of an n-channel inversion mode GaAs MISFET
Author :
Fountain, G.G. ; Rudder, R.A. ; Hattangady, S.V. ; Markunas, R.J. ; Hutchby, J.A.
Author_Institution :
Research Triangle Inst., Research Triangle Park, NC, USA
Abstract :
Summary form only given. An operational GaAs inversion mode n-channel MISFET has been demonstrated using a composite SiO/sub 2/ (15 nm)/Si (1 nm)/GaAs structure. This result is based on an in situ hydrogen cleaning process (used to prepare the GaAs surface just prior to the Si-SiO/sub 2/ deposition), a low-temperature pseudomorphic Si deposition process, and a low-temperature high-quality SiO/sub 2/ deposition process, all performed sequentially in an ultrahigh-vacuum/load locked system. The first working devices exhibit a DC transconductance of 0.26 mS/mm at a gate length and width of 2 mu m and 50 mu m, respectively. Capacitance-voltage analysis of MIS capacitors on chip with the transistors indicates that the midgap electron trap density is on the order of 4*10/sup 11/ cm/sup -2/.<>
Keywords :
III-V semiconductors; electron traps; elemental semiconductors; gallium arsenide; insulated gate field effect transistors; semiconductor-insulator boundaries; silicon; silicon compounds; vacuum deposited coatings; 2 micron; 50 micron; DC transconductance; GaAs-Si-SiO/sub 2/; MIS capacitors; MISFET; capacitance-voltage analysis; gate length; gate width; in situ hydrogen cleaning process; low-temperature pseudomorphic deposition, III-V semiconductors; midgap electron trap density; n-channel inversion mode; ultrahigh-vacuum/load locked system; Electron traps; FETs; Gallium arsenide; Hydrogen; Interface states; MISFETs; Oxidation; Plasma temperature; Surface contamination; Surface treatment;
Conference_Titel :
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1989.74196
