Title :
Novel low-power 1-bit full adder design
Author :
Chen, Chuen-Yau ; Chou, Yung-Pei
Author_Institution :
Dept. of Electr. Eng., Nat. Univ. of Kaohsiung, Kaohsiung, Taiwan
Abstract :
This paper propose a 1-bit low-power full adder that is designed by taking the advantage of the concept of pass-transistor logic and the concept of dual-threshold domino logic. The concept of pass-transistor logic is used to design the circuit generating the sum signal such that the number of transistors can be reduced. The concept of dual-threshold domino logic is adapted to design the circuit generating the carryout signal such that the operation can be speeded up. This full adder was designed with a TSMC 0.18-mum 1P6M CMOS process. The HSPICE simulation results show that this design achieves a superior performance with a power-delay product of 48.98 fJ for the SUM circuit and 16.19 fJ for the CARRYOUT circuit at 1.8-V supply voltage.
Keywords :
CMOS logic circuits; SPICE; adders; carry logic; logic design; low-power electronics; threshold logic; CMOS process; HSPICE simulation; carryout circuit; dual-threshold domino logic; low-power 1-bit full adder design; pass-transistor logic; power-delay product; size 0.18 mum; sum circuit; voltage 1.8 V; Adders; CMOS logic circuits; CMOS technology; Clocks; Energy consumption; Logic circuits; Logic design; MOSFETs; Signal design; Signal generators;
Conference_Titel :
Communications and Information Technology, 2009. ISCIT 2009. 9th International Symposium on
Conference_Location :
Icheon
Print_ISBN :
978-1-4244-4521-9
Electronic_ISBN :
978-1-4244-4522-6
DOI :
10.1109/ISCIT.2009.5341063
