Stacked CMOS inverter with symmetric device performance

Summary form only given. An inherently crystalline monolithic three-dimensional CMOS process was developed. A stacked inverter was built with the footprint of a single transistor. The PMOS transconductance was raised by full-depletion and dual-gate control to match that of an NMOS transistor with the same geometry. The process, which is simpler than that for standard CMOS of equal minimum dimensions, surpasses the latter both in density and device characteristics. Silicon-on-insulator films were realized on preexisting bulk transistors by local epitaxial overgrowth at 830-900 degrees C to minimize dopant diffusion during growth. An inverter with symmetric operation was built using the process described. This technology reduces parasitic capacitances considerably by dielectric insulation. Latchup is completely prevented by the highly doped regions between the complementary devices, yielding high minority carrier recombination rates.<>