DocumentCode :
2503930
Title :
A study of sub-threshold digital circuits for wireless communication systems
Author :
Zainal, Mohd Shamian ; Yoshizawa, Shingo ; Miyanaga, Yoshikazu
Author_Institution :
Grad. Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan
fYear :
2009
fDate :
28-30 Sept. 2009
Firstpage :
1263
Lastpage :
1268
Abstract :
Digital circuit designs in sub-threshold region have been studied in recent years. Their works focus on special purpose for some digital applications in low frequency. This paper proposed modeling analysis of each CMOS logic cell operating at sub-threshold region. We explore the delays and power dissipation of logic cell and make scaled factors mapping from typical voltage to sub-threshold voltage conditions. We evaluated the minimum requirement for 4 bits, 6 bits and 10 bits orthogonal frequency division multiplexing (OFDM) demodulator to operate in sub-threshold region. The simulation results are characteristics of OFDM wireless communication system when it operates at low voltage. It also clearly shows that low voltage is not a barrier for large-scale digital circuits to operate under the threshold voltage.
Keywords :
CMOS logic circuits; OFDM modulation; digital circuits; logic design; radiocommunication; CMOS logic cell; OFDM demodulator; digital circuit design; orthogonal frequency division multiplexing; sub-threshold region; wireless communication system; CMOS logic circuits; Delay; Demodulation; Digital circuits; Low voltage; OFDM; Power dissipation; Power system modeling; Semiconductor device modeling; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications and Information Technology, 2009. ISCIT 2009. 9th International Symposium on
Conference_Location :
Icheon
Print_ISBN :
978-1-4244-4521-9
Electronic_ISBN :
978-1-4244-4522-6
Type :
conf
DOI :
10.1109/ISCIT.2009.5341086
Filename :
5341086
Link To Document :
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