Title :
10 Gb/s clock extraction and data regeneration circuit implemented with phase-locked loop
Author :
Tae-Whan Yoo ; Moon-Soo Park
Author_Institution :
Electron. & Telecommun. Res. Inst., Taejon, South Korea
Abstract :
A PLL clock-extraction and data-regeneration circuit (CEDAR) for 10 Gb/s optical transmission system was realized in a hybrid IC form. The jitter characteristics satisfied the recommendations of ITU-T. The CEDAR compensated against the temperature was tested for the temperature from -10/spl deg/C to 60/spl deg/C and showed no increase of error.
Keywords :
clocks; compensation; hybrid integrated circuits; jitter; optical communication equipment; optical fibre communication; phase locked loops; -10 to 60 degC; 10 Gbit/s; CEDAR; ITU-T recommendations; clock extraction; data regeneration circuit; hybrid IC; jitter characteristics; optical transmission system; phase-locked loop; temperature compensation; Band pass filters; Circuits; Clocks; Data mining; High speed optical techniques; Optical filters; Optical resonators; Optical signal processing; Phase locked loops; Phase shifters;
Conference_Titel :
Microwave Symposium Digest, 1997., IEEE MTT-S International
Conference_Location :
Denver, CO, USA
Print_ISBN :
0-7803-3814-6
DOI :
10.1109/MWSYM.1997.596770
