Scalable core-based methodology and synthesizable core for systematic design environment in multicore SoC (MCSoC)

The strong demand for complex and high performance embedded system-on-chip requires quick turn around design methodology and high performance cores. Thus, there is a clear need for new methodologies supporting efficient and fast design of these systems on complex platforms implementing both hardware and software modules. In this paper, we describe a novel scalable core-based methodology for systematic design environment of application specific heterogeneous multicore systems-on-chip (MC-SoC). We also developed a high performance 32-bit synthesizable QueueCore (QC-2) with single precision floating point support. The core is targeted for special purpose applications within our target MCSoC system. We present the architecture description and design results in a fair amount of details