DocumentCode
2505205
Title
Dynamic analysis of 3 stage Dickson voltage multiplier for an optimized design
Author
Cataldo, C. Di ; Palumbo, Gaetano
Author_Institution
Dipartimento Elettrico Elettronico e Sistemistico, Catania Univ., Italy
fYear
1994
fDate
12-14 Apr 1994
Firstpage
633
Abstract
In this paper we develop dynamic models for an ideal 3 stage Dickson voltage multiplier. Starting from the model proposed, an optimized design can be performed. The circuit discussed is used in a power IC or memory to allow the switching on of an MOS device. The models proposed are validated both by measurement on breadboard and by Spice simulation
Keywords
EPROM; network analysis; network synthesis; power integrated circuits; voltage multipliers; Dickson voltage multiplier; EEPROM; Spice simulation; dynamic analysis; dynamic models; memory; optimized design; power IC; three stage multiplier; Capacitance; Capacitors; Circuit simulation; Clocks; Design optimization; Diodes; Integrated circuit measurements; Power integrated circuits; Switching circuits; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrotechnical Conference, 1994. Proceedings., 7th Mediterranean
Conference_Location
Antalya
Print_ISBN
0-7803-1772-6
Type
conf
DOI
10.1109/MELCON.1994.381011
Filename
381011
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