Title :
Frequency domain topology optimization methodology for a double data rate (DDR) 333 Mbps synchronous DRAM data interface
Author :
Ryu, Woong Hwan ; Fahmy, Hany
Author_Institution :
Intel Corp., Folsom, CA, USA
Abstract :
We propose a novel topology optimization methodology in the frequency domain for a high-speed interface that selects an optimum topology and reduces the time-domain simulation matrix. The method is demonstrated on a DDR333 data interface.
Keywords :
DRAM chips; SRAM chips; circuit optimisation; circuit simulation; frequency-domain analysis; integrated circuit design; network topology; peripheral interfaces; time-domain analysis; 333 Mbit/s; DDR SDRAM data interface; DDR333 data interface; double data rate synchronous DRAM data interface; frequency domain topology optimization methodology; high-speed interface; optimum topology; time-domain simulation matrix; Analytical models; Frequency domain analysis; Optimization methods; Resistors; Resonance; SDRAM; Sensitivity analysis; Time domain analysis; Topology; Transmission line matrix methods;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on
Conference_Location :
Monterey, CA, USA
Print_ISBN :
0-7803-7451-7
DOI :
10.1109/EPEP.2002.1057876
