MPSoC bus architecture optimization under performance constraints for multiple applications

Optimization of interconnects among processors and memories becomes important as multiple processors and memories can be integrated on a Multi-Processor System-on-Chip (MPSoC). Since the optimal interconnection architecture is usually dependent on the application, systematic design methodology for various data transfer requirements is necessary. In this paper, we propose a new optimized bus design methodology under performance constraints. Optimized bus architecture is found to satisfy performance constraints for a single or multiple applications. When compared to unoptimized architectures, our method can reduce the bus switch logic circuits significantly (by more than 50% sometimes). Furthermore, low cost bus architectures can be found to satisfy the performance constraints for a set of given applications.