• DocumentCode
    2505570
  • Title

    Distributed circuit models for near-CSP interconnects

  • Author

    Chandrasekhar, Arun ; Beyne, Eric ; De Raedt, Walter ; Nauwelaers, Bart

  • Author_Institution
    Departement Elektrotechniek, Katholieke Univ., Leuven, Belgium
  • fYear
    2002
  • fDate
    21-23 Oct. 2002
  • Firstpage
    63
  • Lastpage
    66
  • Abstract
    At frequencies beyond 1 GHz, there is a large difference between the on-chip and off-chip performance, since the package behaves as a passive element and influences the electrical behaviour. An accurate model of the package is necessary to predict this off-package behaviour and it serves as an input to the chip designer for \´chip-package co-design\´. However, this is not the only requirement from the model. With chip scale packages being re-designed for different RF applications, the package model is expected to accommodate the variable physical dimensions as model parameters - in other words, be scalable. Several papers in the literature use simple and complex lumped element models to represent package interconnections (Z. Yang et al, WESCON/\´95, pp. 106-110, 1995; M.F. Caggiano et al, Proc. 48th IEEE ECTC, pp. 1280-1285, 1998) but there are a number of simple distributed models as well (C.Y. Chung, Proc. 47th IEEE ECTC, pp. 304-309, 1997). However, H. Liang et al (Microwave Symp. Dig., IEEE MTT-S Int., vol. 1, pp. 65-68, 2000) proposed a preliminary "hybrid circuit model" for the BGA transition. For lumped element models, apart from suffering from loss of accuracy at high frequencies, it is almost impossible to study the effect of individual components in the overall package interconnect. In this work, we have developed distributed circuit models for two near-CSPs, namely the polymer stud grid array (PSGA) and the ball grid array (BGA). The differences in the model topology are due to the approaches used for the package routing and consequently the mode of signal propagation. Apart from achieving excellent accuracy up to 8 GHz, both the models can be scaled for changes in the physical dimensions of the package interconnect.
  • Keywords
    ball grid arrays; chip scale packaging; circuit analysis computing; integrated circuit interconnections; integrated circuit measurement; integrated circuit modelling; network routing; network topology; plastic packaging; BGA transition; PSGA; RF applications; ball grid array; chip scale packages; chip-package co-design; distributed circuit models; distributed models; electrical behaviour; hybrid circuit model; individual component effects; lumped element models; model parameters; model topology; near-CSP interconnects; off-chip performance; on-chip performance; package interconnect physical dimensions; package model; package passive element behaviour; package physical dimensions; package routing; polymer stud grid array; scalable models; signal propagation mode; Chip scale packaging; Integrated circuit interconnections; Probes; Radio frequency; Routing; Scalability; Semiconductor device measurement; Substrates; Testing; Uniform resource locators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on
  • Conference_Location
    Monterey, CA, USA
  • Print_ISBN
    0-7803-7451-7
  • Type

    conf

  • DOI
    10.1109/EPEP.2002.1057884
  • Filename
    1057884