The influence of cell library characteristics on power consumption of CMOS circuits

The design and the implementation of low power digital devices has become of extreme importance; therefore, the problem of reducing the power dissipated by CMOS circuits has been addressed on several fronts. Current research has focused on architectural and technological transformations, re-implementation of logic synthesis procedures, and modification of technology mapping algorithms to produce low power circuits; although the results obtained so far are very encouraging, there is one aspect of the overall synthesis process which has not been faced with enough care: the design of cell libraries to be used for the realization of the synthesized design. The authors present a discussion and some experimental data concerning the impact that cell library characteristics may have on the power consumption of CMOS devices