Title :
New sample-and-hold for high frequency applications
Author :
Cataldo, C. Di ; Palmisano, C. ; Palumbo, Gaetano
Author_Institution :
Dipartimento Elettrico Elettronico e Sistemistico, Catania Univ., Italy
Abstract :
Presents a novel fast and accurate sample-and-hold (S/H) circuit which can be designed using conventional low-gain amplifiers. Moreover, the offset contribution to the output voltage is intrinsically compensated for and the clock-feedthrough error can be reduced by slightly changing the clock scheme. In order to validate its performance, the proposed S/H circuit was implemented using a single-stage differential amplifier with current mirror active load and simulated with the model parameters of a standard 2-μm CMOS process
Keywords :
CMOS analogue integrated circuits; SPICE; differential amplifiers; integrated circuit design; sample and hold circuits; 1.2 micron; CMOS process; SPICE simulation; clock scheme; clock-feedthrough error; conventional low-gain amplifiers; current mirror active load; high frequency applications; offset contribution; output voltage; performance; sample-and-hold circuit; single-stage differential amplifier; Capacitors; Circuit simulation; Clocks; Differential amplifiers; Frequency; Mirrors; Poles and zeros; Switches; Switching circuits; Voltage;
Conference_Titel :
Electrotechnical Conference, 1994. Proceedings., 7th Mediterranean
Conference_Location :
Antalya
Print_ISBN :
0-7803-1772-6
DOI :
10.1109/MELCON.1994.381040
