Development of an organic micromachined isolation scheme for wafer-level packaging

Author

Venkateshan, A. ; Pham, A. ; Harriss, J.

Author_Institution

Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA

fYear

2002

fDate

21-23 Oct. 2002

Firstpage

111

Lastpage

114

Abstract

We present the design and development of an isolation scheme for highly integrated RF transceivers on a chip. The on-chip isolation structure consists of a 700 /spl mu/m micromachined SU-8 bar and a 100 /spl mu/m V-groove etched beneath a 475 /spl mu/m silicon substrate. We have achieved a measured cumulative isolation of more than 30 dB up to 4 GHz. A variety of backside etch profiles which will further improve the isolation are also to be presented.

Keywords

etching; integrated circuit design; integrated circuit packaging; isolation technology; micromachining; transceivers; 100 micron; 4 GHz; 475 micron; 700 micron; Si; backside etch profiles; cumulative isolation; etched V-groove; integrated RF transceivers; isolation scheme design; micromachined SU-8 bar; on-chip isolation structure; organic micromachined isolation scheme; silicon substrate; wafer-level packaging; Circuits; Etching; Gold; Metallization; Micromachining; Radio frequency; Silicon; Transceivers; Transmitters; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on

Conference_Location

Monterey, CA, USA

Print_ISBN

0-7803-7451-7

Type

conf

DOI

10.1109/EPEP.2002.1057895

Filename

1057895