Optimal thermal characterization of a stacked die package with TSV technology

Through silicon via (TSV) technology is one of the most rapidly developing technologies in the semiconductor industries and assures the development for the continued role of Moore´s law and multichip integration as well as packaging approaches. Wire bond and flip-chip have been in use for long time now while TSV is the latest technology of 3D integration system which is used for primary interconnection. The benefits of the use of TSV technology are increased performance, reduced form factor, cost reduction of the package etc. A steady state thermal analysis is carried out of a stacked die package using through silicon vias technology to minimize maximum junction temperature for the various set of geometric and process parameters. A three dimensional finite element model (octant model) of a stacked package that consists of stacked dice, solder interconnect substrate, underfill, through silicon vias and PWB is solved numerically to minimize the junction temperature of the stacked package. A parametric study consists of critical geometric and process parameters such as aspect ratio (configuration of vias structure), underfill thickness, underfill thermal conductivity and convection heat transfer coefficient (h) applied on the top of mold cap. Recommendations are provided regarding the development of design guidelines for through silicon vias structure which can have impact on geometric as well as material configuration in keeping junction temperature within limit.