Engineering the effective CTE of Si die with a T2 package

With the continuous scaling of low k dielectric in multicore processors, the intrinsic CTE mismatch between a Si die (CTE: 2.3 ppm/°C) and an organic substrate (16-18 ppm/°C) brings a susceptibility for more failures. There are limited successes in the engineering of the CTE of substrate with ceramic (~6 ppm/°C) or low CTE organic substrates (~12 ppm/°C). The CTE mismatch also contributes to solder joint reliability risks and misalignment in assembly. In this paper, we propose a very different method to address the CTE mismatch: the effective CTE of Si is engineered to match that of an organic substrate instead. The T2 package with both thinner die and thinner thermal interface material (TIM) is proposed as both a mechanical and thermal solution for electronic packages. Experimental measurement using DIC (digital image correlation) shows that the effective CTE of silicon can be as high as 15-16 ppm/°C. Thus, it reduces the mismatch between the silicon die and the organic substrate from roughly 15 ppm/°C to 1-3 ppm/°C. Moiré measurement shows the corner stress reduction and the temperature cycle study proves the effectiveness of CTE engineering. Thermomechanical simulations and reliability studies with different Si die thicknesses are also reported.