A CAD tool for Stochastic Macromodel generation and analog IP characterization for system level application

Process variations have increased significantly with scaling technologies. This has led to deviations in analog circuit performance from their expected values. Macromodeling of analog circuits is emerging to be an essential paradigm of CAD, leading to significant benefits for simulation, design space exploration, inter process migration, test development etc. In this work, we develop a CAD tool for automatic generation of macromodels from available specifications and extend the methodology to model the effect of process variation induced soft parametric faults. Simulation results illustrate that the methodology is suitable for accurate macromodeling with objective of rapid simulation. In addition, the performance of circuits under process variation can be effectively statistically modeled for the estimation of system level yield.