DocumentCode :
2506123
Title :
Buried solder bump connections for high-density capacitive coupling
Author :
Mick, Stephen ; Luo, Lei ; Wilson, John ; Franzon, Paul
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
fYear :
2002
fDate :
21-23 Oct. 2002
Firstpage :
205
Lastpage :
208
Abstract :
AC coupled interconnects enable reliable, multi-gigabit-per-second communication data rates between integrated circuits with very high pin counts and low power consumption. When used in conjunction with NRZ-tolerant receivers, interconnect arrays with pitches below 100 /spl mu/m and data rates of 6 Gbps/per pin can be built.
Keywords :
CMOS integrated circuits; VLSI; capacitance; fine-pitch technology; integrated circuit interconnections; multichip modules; soldering; 100 micron; 6 Gbit/s; AC coupled interconnects; CMOS VLSI chips; MCM; NRZ-tolerant receivers; buried solder bump connections; high data rate interconnection; high pin counts; high-density capacitive coupling; integrated circuits; interconnect arrays; low power consumption; multi-Gbit/s communication data rates; multichip module; CMOS process; CMOS technology; Capacitors; Coupling circuits; Fabrication; Integrated circuit interconnections; Integrated circuit reliability; Packaging; Parasitic capacitance; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on
Conference_Location :
Monterey, CA, USA
Print_ISBN :
0-7803-7451-7
Type :
conf
DOI :
10.1109/EPEP.2002.1057916
Filename :
1057916
Link To Document :
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